In the field of electronics, one of the most sought after goals is miniaturization. Efforts to make electronics and electronic memory smaller continue to drive manufacturers. There are a variety of techniques and technologies that facilitate continued miniaturization. One technique that is growing in importance is the deep etching of wafers, and the volume of wafers that go through this process is increasing. As the lateral dimensions of the etched features on a wafer, including etched features, continue to decrease, the ability to control the etching process is becoming more difficult.
For companies that make wafers with narrow deep etches, if the aspect ratio, which is defined as the ratio of etched depth to etched width, is more than approximately 5:1, optical non-contact measurement techniques are typically not viable. The reason for this is because optical technologies are not able to receive information from the bottom of an etched feature when viewed from the top. For example, if the width of the etched feature (also referred to as a trench or a via) is smaller than the illumination spot size, then the etched opening itself restricts the amount of light that can illuminate the bottom. However, if the illuminating spot is made smaller by increasing the numerical aperture of the illuminating optics, then the angular spectrum of the illumination will contain light rays at angles to steep to illuminate the bottom of the etched feature. As a result, when the aspect ratio is large and the etched width is small, there is no way to direct a significant portion of the illuminating light on the bottom of the etched feature. Therefore, an engineer who is utilizing the process must take measurements from a scanning electron microscope. These measurements are typically costly, time consuming and most importantly, destructive.
One of the most important electronic devices is a semiconductor, and one of the primary elements of a semiconductor is a silicon on insulator (SOI) wafer. During the manufacturing of electronic devices on a semiconductor wafer, some wafers go through a process known as thinning. There are a variety of reasons why a wafer must be thinned, but the most common are: to dissipate heat quickly, to expose interconnect layers, and to produce the silicon on insulator (SOI) wafer. SOI wafers are comprised of a thin layer of silicon on top of a thin layer of insulator, and these layers are supported by a full thick silicon wafer. Currently, approximately 5% of all semiconductor wafers manufactured are SOI wafers, but this percentage will continue to increase in the fixture.
The most widely used methods for thinning a wafer are back grinding and polishing. These methods operate on the lower surface, i.e. the non-etched surface, of the wafer. Wafer manufacturers must grind or polish the lower surface of the wafer to the desired thickness with high uniformity. If the wafer is lapped too thin, it might lack the required structural integrity or the interconnects will be overexposed. Even so, the industry trend is directed toward the manufacturing of consistently thinner wafers.
Another important aspect of semiconductor manufacturing is the measurement of wafer thickness. Present technology for measuring wafer thickness includes capacitive sensors, which measure the capacitance of a wafer, and height sensor techniques that utilize two sensors, with one sensor above the wafer and one sensor below the wafer. The use of capacitive sensors typically requires an in-depth knowledge of the wafer material and can generally only function correctly with a single wafer material, not wafers composed of multiple layers of different materials, such as SOI wafers, wafers supported by carriers or handle wafers. Additionally, capacitive sensors have a lower thickness limit of approximately 200 microns and are limited to a small sample of materials.
Height sensor techniques can generally function on thinner samples, and can accommodate multiple layer wafer stacks that are made of virtually any material as they detect the physical surface of a wafer. Height sensor techniques do require delicate alignment in all three axes and require calibration to “teach” the sensor how far apart the axes are in space. This calibration requirement is the lower accuracy limit of the measurements taken.
Present and developing technology for the connection of electronic chips of various functions includes a process known as Through Silicon Vias (TSVs). A TSV is essentially a small cavity in a silicon wafer, with a typical diameter of 1 to 100 microns and a typical depth of 25 to 500 microns. These etched features, as well as others such as trenches, are known as High Aspect Ratio features because their depth is significantly greater than their width. The TSVs are typically filled with a conductive material and then the electronic chips are built on top of the TSVs. When the chips are complete, the wafer is polished, or thinned, from the lower surface until the TSVs are exposed. The TSVs then facilitate the connections that are made to other chips or devices.
During the wafer manufacturing process, the depth of the TSVs is a critical element. If the TSVs are not deep enough, the wafer will not maintain the physical integrity that is required to continue the process when the TSVs are exposed. If the TSVs are too deep, they will be exposed before the wafer is thin enough. A manufacturing process engineer has no means of quickly, accurately and non-destructively measuring the thickness of a wafer during the manufacturing process. Currently, a wafer is thinned until visual inspection confirms the TSVs are exposed, without possessing accurate knowledge of the thickness of the wafer.
There are a variety of requirements for measuring the depth of an etched feature on a wafer. The high aspect ratio etched features are difficult to measure when using optical techniques because light can not propagate to the bottom of an etched feature and then return. This applies to both confocal techniques as well as interferometric techniques. Optical techniques are limited to an aspect ratio of 2 or 3 to 1. For etched features with a higher aspect ratio, the only current method to directly measure the depth is by destructively sectioning the wafer and then viewing the etched feature from the side. This method is undesirable because the wafer sample is destroyed and the electron microscope that must be utilized is expensive and time consuming.
Another wafer thinning process occurs for Silicon On Insulator (501) applications. SOI is essentially a wafer stack that comprises the fusing of two wafers with a thin oxide layer between the two wafers. The first wafer, which is known as the device wafer, is then polished to a specific thickness. The second wafer, which is known as the handle wafer, is sacrificial and is used simply to maintain the structural integrity of the device wafer.
Current technology only measures the entire wafer stack and can not differentiate between the two wafers. Therefore, a process engineer must measure the first/handle wafer, measure the oxide layer and then subtract these measurements in order to calculate the thickness of the second/device layer. The sensor utilized in the instant invention can differentiate between the two wafers and can measure the first/device layer directly, thereby reducing the error budget and improving accuracy.
A search of the prior art did not disclose literature or patents that read directly on the claims of the instant invention. However, the following U.S. patents are considered related.
PAT. NO.INVENTORISSUEDUS2007/0148792(Pub)Marx, et al28 Jun. 20076,878,301Mundt12 Apr. 20056,822,745DeGrout, et al23 Nov. 20046,806,105Johnson, et al19 Oct. 2004
The US2007/0148792 Publication discloses a system for measuring wafer thickness, flatness and the depth of etched features thereon. The system utilizes the non-etched surface of the wafer to accurately measure the lower surface of an etched feature, rendering the etched feature an effective bump that can be measured on the etched surface and non-etched surface by using a non-contact optical instrument. The system discloses the use of distance measuring sensors such as a chromatic confocal sensor to measure the trench, as a bump. The system utilizes a light source that renders the material of which the wafer is composed transparent. The light source functions in the near infrared region for measuring the thickness and trench depth of wafers made of silicon, which is opaque in the visible region and transparent in the rear infrared region. The difference between the referenced publication and the instant application is that the referenced publication uses distance measuring sensors, whereas the instant application uses a reflectometer.
The U.S. Pat. No. 6,878,301 discloses a method and an apparatus for optically detecting a trench's depth by detecting a first maxima in an intensity of multi-wavelength light. A portion of the multi-wavelength light is reflected from the trench's top surface. A second maxima in an intensity of multi-wavelength light is also detected. A portion of the multi-wavelength light is reflected from the trench's bottom surface. A maxima peak separation between the first maxima and the second maxima is determined which corresponds to the maxima peak separation. The apparatus is essentially a Michelson interferometer, and as such, requires a reference mirror. Additionally, the method disclosed illuminates the wafer on the etched surface.
The U.S. Pat. No. 6,822,745 discloses a method for determining a geometric property of a test object. The method includes interferometrically profiling a first surface of the test object in a first coordinate system; interferometrically profiling a second surface of the test object in a second coordinate system that is different from the first coordinate system; and providing a relationship between the first and second coordinate system. The geometric property is calculated based on the interferometrically profiled surfaces and the relationship between the first and second coordinate system.
The U.S. Pat. No. 6,806,105 discloses a method for measuring a parameter associated with a portion of a sample. The sample has formed thereon one or more structures with at least two zones each having an associated zone reflectance property. The method includes illuminating the zones with broadband light, and measuring at least one reflectance property of light reflected from the two zones. The method includes fitting a parametric model to the measured reflectance property. The parametric model mixes the reflectance properties of the zones to account for partially coherent light interactions between the two zones.